Innovations in semiconductor fabrication and packaging technologies have enabled development of high performance, densely integrated semiconductor chip modules. The downscaling of chip geometries and the increase in operating speeds lead to increased power densities, resulting in more heat generation per unit area. The increased power density poses practical limitations to the level of integration density and performance that may be achieved. The ability to implement chip modules with higher densities and higher performance is limited primarily by the ability to effectively cool the chip modules during normal operation. For instance, as heat is generated by integrated circuit (“IC”) chips during normal operation, cooling structures must be employed to provide sufficiently low thermal resistance paths between the chips and ambient air or a circulating liquid coolant to adequately remove heat and maintain the operating temperature of the chips low enough to assure continued reliable operation.
In conventional packaging technologies, chip level packages can be constructed with one or more chips mounted on a thin flexible first level package substrate, such as an organic laminate build up package substrate, using micro solder bump connections, referred to as C4's (controlled collapse chip connection). The packages are often bonded to a cap, which provides structural stability to the package by reducing warpage, and by spreading heat along a plane, thereby improving the package thermal performance. The cap, in turn, is attached to a secondary cooling structure, such as a heat sink or a liquid cooling system.
Referring now to FIG. 1, a flip chip ball grid array (BGA) package 100, according to the prior art, comprises a chip die 112 having an operational surface mounted onto a substrate 106 via a series of C4's 108 encased in an underfill layer 110. These components are operatively connected to a circuit board 102 via a separate series of solder balls 104. The die 112 is said to be flipped because its operational connections face down towards the substrate 106 and the circuit board 102, and its other side is connected to a heat sink 140 via a protective heat spreading cap 114. Several layers of the package 100 are connected using layers of material, including, for example, the thermal interface material (TIM1) 132 connecting the die 112 to the cap 114, the adhesive layer 130 connecting the cap 114 to the substrate 106, and the thermal interface material (TIM2) 134 connecting the cap 114 the heat sink 140.
In conventional implementations, the heat spreading cap 114 may be made from copper, having a thermal conductivity of 400 W/m-° C., at 300° K. Although copper has relatively high structural stability and extends that stability to the package 100, it is not the most thermally conductive material available. Some forms of graphite, for example, have much higher thermal conductivity across at least one spatial plane. Other forms of graphite exhibit thermal conductivity above 1200 W/m-° C. These materials generally are referred to as high-k materials, or high-k graphite.
According to an aspect of the prior art (for example, as disclosed by U.S. Pat. No. 6,758,263 B2 entitled “HEAT DISSIPATING COMPONENT USING HIGH CONDUCTIVE INSERTS”), a heterogeneous planar graphite element includes a high-conductivity graphite layer having a cavity for housing an insert. The graphite layer exhibits high thermal conductivity in the x and y planes, but low thermal conductivity in the z plane. The insert layer has relatively higher thermal conductivity across the z plane, but not across the x or y planes.
Traditional designs and methods in the prior art face significant challenges, particularly because known structures using high-k material exhibit weak structural stability, and experience warpage under normal operating temperatures. This warpage leads to device defects and even to device failure. In fact, the relative instability of these structures also makes more prone to damage during manufacturing processes. Furthermore, prior art solutions using graphite employ one or more heterogeneous layers, adding to device complexity but taking advantage of graphite's thermal conductivity in a limited way.
Therefore, it is desirable to manage heat spreading and dissipation in semiconductor packaging technology by taking advantage of the relatively high thermal conductivity of available material, such as graphite, while at the same time maintaining structural integrity of the package and its constituent components.